The present disclosure relates to technology for non-volatile storage. Techniques for erasing non-volatile storage are described.
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in personal navigation devices, cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate and channel regions are positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
The memory cells in some EEPROMs or flash memory devices are arranged as strings. For example, some have a configuration referred to as a NAND configuration in which memory cells are grouped as NAND strings with each NAND string associated with a bit line. A NAND string includes numerous memory cells and a select gate at each end, in one implementation. A group of NAND strings may each be associated with a number of word lines that are used to apply control voltages to control gates of the memory cells. Also the group may be associated with select lines that are used to apply control voltages to the select gates.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state.
In some implementations, the memory cells are erased prior to programming. For some architectures, erasing can be performed on the entire memory array, on individual blocks, or another unit of cells. In one implementation, a group of memory cells is erased by raising p-wells of the memory cells to an erase voltage for a sufficient period of time. Word lines may be grounded when applying the erase voltage. An erase pulse moves the threshold voltage of the memory cells towards (or beyond) an erase target level, which may be below 0 Volts. In some implementations, after applying the erase pulse, an erase verify operation is performed to determine whether the threshold voltages of the memory cells have at least reached the erase target level. The erase pulse and erase verify are repeated with each loop using a higher amplitude erase pulse until the erase verify passes.